// Xilinx XPort Language Converter, Version 4.1 (110)
// 
// ABEL    Design Source: LED_8BIT.abl
// Verilog Design Output: LED_8BIT.v
// Created 15-May-2014 12:23 AM
//
// Copyright (c) 2014, Xilinx, Inc.  All Rights Reserved.
// Xilinx Inc makes no warranty, expressed or implied, with respect to
// the operation and/or functionality of the converted output files.
// 

module LED_8BIT(CLK, IDSEL, FRAME, IRDY, TRDY, DEVSEL, STOP, RST, CBE3, CBE2,
      CBE1, CBE0, AD3, AD2, LED_A3, LED_A2, LED_A1, LED_A0, LED_B3, LED_B2,
      LED_B1, LED_B0, DEBUG);
   input CLK, IDSEL, FRAME, IRDY, RST, CBE3, CBE2, CBE1, CBE0;
   output TRDY, DEVSEL, STOP, AD3, AD2, LED_A3, LED_A2, LED_A1, LED_A0, LED_B3,
	 LED_B2, LED_B1, LED_B0, DEBUG;

   wire FRAME_REG, CBE_REG3, CBE_REG2, CBE_REG1, CBE_REG0, AD_REG3, AD_REG2,
	 FRAME_START, ST0, ST1, ST2, WR_READY, LED_REG7, LED_REG6, LED_REG5,
	 LED_REG4, LED_REG3, LED_REG2, LED_REG1, LED_REG0, RD_ACTIVE3,
	 RD_ACTIVE2, RD_ACTIVE1, RD_ACTIVE0, AD_OE, TGT_OE, FRAME_REG_CLK,
	 ST0_CLR, ST1_CLR, ST2_CLR, DEVSEL_OE, TRDY_OE, STOP_OE, RD_ACTIVE0_CE,
	 RD_ACTIVE1_CE, RD_ACTIVE2_CE, RD_ACTIVE3_CE, RD_ACTIVE0_D,
	 RD_ACTIVE1_D, RD_ACTIVE2_D, RD_ACTIVE3_D, LED_REG0_D, LED_REG1_D,
	 LED_REG2_D, LED_REG3_D, LED_REG4_D, LED_REG5_D, LED_REG6_D,
	 LED_REG7_D, ST2_D, ST1_D, ST0_D, AD_REG2_D, AD_REG3_D, CBE_REG0_D,
	 CBE_REG1_D, CBE_REG2_D, CBE_REG3_D, FRAME_REG_D, AD3_ZD, AD2_ZD,
	 STOP_ZD, TRDY_ZD, DEVSEL_ZD, AD2_OE_ctrl, RD_ACTIVE0_ACLR_ctrl,
	 RD_ACTIVE0_CLK_ctrl, LED_REG0_CLK_ctrl, LED_REG0_CE_ctrl,
	 LED_REG2_CE_ctrl, LED_REG4_CE_ctrl, LED_REG6_CE_ctrl, ST0_CLK_ctrl,
	 ST1_CE_ctrl, AD_REG2_CE_ctrl, AD_REG2_CLK_ctrl, CBE_REG0_CE_ctrl,
	 CBE_REG0_CLK_ctrl;
   reg RD_ACTIVE0_FB, RD_ACTIVE1_FB, RD_ACTIVE2_FB, RD_ACTIVE3_FB, LED_REG0_FB,
	 LED_REG1_FB, LED_REG2_FB, LED_REG3_FB, LED_REG4_FB, LED_REG5_FB,
	 LED_REG6_FB, LED_REG7_FB, ST2_FB, ST1_FB, ST0_FB, AD_REG2_FB,
	 AD_REG3_FB, CBE_REG0_FB, CBE_REG1_FB, CBE_REG2_FB, CBE_REG3_FB,
	 FRAME_REG_FB;

   // initial {RD_ACTIVE0_FB, RD_ACTIVE1_FB, RD_ACTIVE2_FB, RD_ACTIVE3_FB,
   //       LED_REG1_FB, LED_REG2_FB, LED_REG6_FB, LED_REG7_FB, ST2_FB,
   //       ST1_FB, ST0_FB, AD_REG2_FB, AD_REG3_FB, CBE_REG0_FB, CBE_REG1_FB,
   //       CBE_REG2_FB, CBE_REG3_FB, FRAME_REG_FB} = 18'h0;

   // initial {LED_REG0_FB, LED_REG3_FB, LED_REG4_FB, LED_REG5_FB} = 4'hf;

   assign AD2 = (AD2_OE_ctrl) ? AD2_ZD : 1'bz;
   assign AD3 = (AD2_OE_ctrl) ? AD3_ZD : 1'bz;
   assign STOP = (STOP_OE) ? STOP_ZD : 1'bz;
   assign DEVSEL = (DEVSEL_OE) ? DEVSEL_ZD : 1'bz;
   assign TRDY = (TRDY_OE) ? TRDY_ZD : 1'bz;

   assign FRAME_REG = FRAME_REG_FB;
   always @(posedge FRAME_REG_CLK)
      FRAME_REG_FB <= FRAME_REG_D;

   assign {CBE_REG3, CBE_REG2, CBE_REG1, CBE_REG0} = {CBE_REG3_FB, CBE_REG2_FB,
	 CBE_REG1_FB, CBE_REG0_FB};
   always @(posedge CBE_REG0_CLK_ctrl)
      if (CBE_REG0_CE_ctrl)
	 {CBE_REG3_FB, CBE_REG2_FB, CBE_REG1_FB, CBE_REG0_FB} <= {CBE_REG3_D,
	       CBE_REG2_D, CBE_REG1_D, CBE_REG0_D};

   assign {AD_REG3, AD_REG2} = {AD_REG3_FB, AD_REG2_FB};
   always @(posedge AD_REG2_CLK_ctrl)
      if (AD_REG2_CE_ctrl)
	 {AD_REG3_FB, AD_REG2_FB} <= {AD_REG3_D, AD_REG2_D};

   assign ST0 = ST0_FB;
   always @(posedge ST0_CLK_ctrl)
      ST0_FB <= ST0_D & (!ST0_CLR);

   assign {ST1, ST2} = {ST1_FB, ST2_FB};
   always @(posedge ST0_CLK_ctrl)
      if (ST1_CE_ctrl)
	 {ST1_FB, ST2_FB} <= {ST1_D & (!ST1_CLR), ST2_D & (!ST2_CLR)};

   assign {LED_REG7, LED_REG6} = {LED_REG7_FB, LED_REG6_FB};
   always @(posedge LED_REG0_CLK_ctrl)
      if (LED_REG6_CE_ctrl)
	 {LED_REG7_FB, LED_REG6_FB} <= {LED_REG7_D, LED_REG6_D};

   assign {LED_REG5, LED_REG4} = {LED_REG5_FB, LED_REG4_FB};
   always @(posedge LED_REG0_CLK_ctrl)
      if (LED_REG4_CE_ctrl)
	 {LED_REG5_FB, LED_REG4_FB} <= {LED_REG5_D, LED_REG4_D};

   assign {LED_REG3, LED_REG2} = {LED_REG3_FB, LED_REG2_FB};
   always @(posedge LED_REG0_CLK_ctrl)
      if (LED_REG2_CE_ctrl)
	 {LED_REG3_FB, LED_REG2_FB} <= {LED_REG3_D, LED_REG2_D};

   assign {LED_REG1, LED_REG0} = {LED_REG1_FB, LED_REG0_FB};
   always @(posedge LED_REG0_CLK_ctrl)
      if (LED_REG0_CE_ctrl)
	 {LED_REG1_FB, LED_REG0_FB} <= {LED_REG1_D, LED_REG0_D};

   assign RD_ACTIVE3 = RD_ACTIVE3_FB;
   always @(posedge RD_ACTIVE0_CLK_ctrl or posedge RD_ACTIVE0_ACLR_ctrl)
      if (RD_ACTIVE0_ACLR_ctrl)
	 RD_ACTIVE3_FB <= 1'h0;
      else
	 if (RD_ACTIVE3_CE)
	    RD_ACTIVE3_FB <= RD_ACTIVE3_D;

   assign RD_ACTIVE2 = RD_ACTIVE2_FB;
   always @(posedge RD_ACTIVE0_CLK_ctrl or posedge RD_ACTIVE0_ACLR_ctrl)
      if (RD_ACTIVE0_ACLR_ctrl)
	 RD_ACTIVE2_FB <= 1'h0;
      else
	 if (RD_ACTIVE2_CE)
	    RD_ACTIVE2_FB <= RD_ACTIVE2_D;

   assign RD_ACTIVE1 = RD_ACTIVE1_FB;
   always @(posedge RD_ACTIVE0_CLK_ctrl or posedge RD_ACTIVE0_ACLR_ctrl)
      if (RD_ACTIVE0_ACLR_ctrl)
	 RD_ACTIVE1_FB <= 1'h0;
      else
	 if (RD_ACTIVE1_CE)
	    RD_ACTIVE1_FB <= RD_ACTIVE1_D;

   assign RD_ACTIVE0 = RD_ACTIVE0_FB;
   always @(posedge RD_ACTIVE0_CLK_ctrl or posedge RD_ACTIVE0_ACLR_ctrl)
      if (RD_ACTIVE0_ACLR_ctrl)
	 RD_ACTIVE0_FB <= 1'h0;
      else
	 if (RD_ACTIVE0_CE)
	    RD_ACTIVE0_FB <= RD_ACTIVE0_D;

// Start of original equations
   assign FRAME_REG_D = FRAME;
   assign FRAME_REG_CLK = CLK;
   assign FRAME_START = FRAME_REG & (!FRAME) & IDSEL & ({CBE3, CBE2, CBE1,
	 CBE0} == 4'b1010 | {CBE3, CBE2, CBE1, CBE0} == 4'b1011);
   assign {CBE_REG3_D, CBE_REG2_D, CBE_REG1_D, CBE_REG0_D} = {CBE3, CBE2, CBE1,
	 CBE0};
   assign CBE_REG0_CLK_ctrl = CLK;
   assign CBE_REG0_CE_ctrl = FRAME_START;
   assign {AD_REG3_D, AD_REG2_D} = {AD3, AD2};
   assign AD_REG2_CLK_ctrl = CLK;
   assign AD_REG2_CE_ctrl = FRAME_START;
   assign ST0_D = FRAME_START & {CBE3, CBE2, CBE1, CBE0} == 4'b1010 &
	 {RD_ACTIVE3, RD_ACTIVE2, RD_ACTIVE1, RD_ACTIVE0} == 4'b1111;
   assign ST1_D = ST0 | (FRAME_START & {CBE3, CBE2, CBE1, CBE0} == 4'b1011);
   assign ST2_D = ST1;
   assign ST1_CE_ctrl = (!ST1) | (!IRDY);
   assign {ST2_CLR, ST1_CLR, ST0_CLR} = {3{FRAME & IRDY}};
   assign ST0_CLK_ctrl = CLK;
   assign TGT_OE = ST1 | ST2;
   assign DEVSEL_ZD = !ST1;
   assign DEVSEL_OE = TGT_OE;
   assign TRDY_ZD = !ST1;
   assign TRDY_OE = TGT_OE;
   assign STOP_ZD = !ST1;
   assign STOP_OE = TGT_OE;
   assign {LED_A3, LED_A2, LED_A1, LED_A0, LED_B3, LED_B2, LED_B1, LED_B0} =
	 {LED_REG7, LED_REG6, LED_REG5, LED_REG4, LED_REG3, LED_REG2, LED_REG1,
	 LED_REG0};
   assign WR_READY = ST1 & (!IRDY) & {CBE_REG3, CBE_REG2, CBE_REG1, CBE_REG0}
	 == 4'b1011;
   assign {LED_REG7_D, LED_REG6_D, LED_REG5_D, LED_REG4_D, LED_REG3_D,
	 LED_REG2_D, LED_REG1_D, LED_REG0_D} = {AD3, AD2, AD3, AD2, AD3, AD2,
	 AD3, AD2};
   assign LED_REG6_CE_ctrl = WR_READY & {AD_REG3, AD_REG2} == 2'b11;
   assign LED_REG4_CE_ctrl = WR_READY & {AD_REG3, AD_REG2} == 2'b10;
   assign LED_REG2_CE_ctrl = WR_READY & {AD_REG3, AD_REG2} == 2'b01;
   assign LED_REG0_CE_ctrl = WR_READY & {AD_REG3, AD_REG2} == 2'b00;
   assign LED_REG0_CLK_ctrl = CLK;
   assign {RD_ACTIVE3_D, RD_ACTIVE2_D, RD_ACTIVE1_D, RD_ACTIVE0_D} = 4'b1111;
   assign RD_ACTIVE0_CE = WR_READY & {AD_REG3, AD_REG2} == 2'b00;
   assign RD_ACTIVE1_CE = WR_READY & {AD_REG3, AD_REG2} == 2'b01;
   assign RD_ACTIVE2_CE = WR_READY & {AD_REG3, AD_REG2} == 2'b10;
   assign RD_ACTIVE3_CE = WR_READY & {AD_REG3, AD_REG2} == 2'b11;
   assign RD_ACTIVE0_CLK_ctrl = CLK;
   assign RD_ACTIVE0_ACLR_ctrl = !RST;
   assign {AD3_ZD, AD2_ZD} = ({2{{AD_REG3, AD_REG2} == 2'b00}} & {LED_REG1,
	 LED_REG0}) | ({2{{AD_REG3, AD_REG2} == 2'b01}} & {LED_REG3, LED_REG2})
	 | ({2{{AD_REG3, AD_REG2} == 2'b10}} & {LED_REG5, LED_REG4}) |
	 ({2{{AD_REG3, AD_REG2} == 2'b11}} & {LED_REG7, LED_REG6});
   assign AD2_OE_ctrl = AD_OE;
   assign AD_OE = ST1 & {CBE_REG3, CBE_REG2, CBE_REG1, CBE_REG0} == 4'b1010 &
	 {RD_ACTIVE3, RD_ACTIVE2, RD_ACTIVE1, RD_ACTIVE0} == 4'b1111;
   assign DEBUG = FRAME_START;
endmodule